Next: 1.0 Introduction Up: Appnotes Index Previous:Appnote DFT Index

1.0 Executive Summary

• 1.1 The Design For Test (DFT) Methodology - Complete Life Cycle Testability Support
• 1.2 The DFT Application Process - Tools and Design Element Reuse
• 1.3 Summary of DFT Contribution to RASSP

2.0 Introduction

3.0 Technology Description

4.0 Application Example

• 4.1 Problem Definition and Approach to Solution
• 4.2 Stepwise Application of Methodology
  • 4.2.1 Dependency Modeling to Support Architecture Selection
  • 4.2.2 Collection and Specification of Requirements
  • 4.2.3 Requirements Consolidation and Test Strategy Selection - Singular Test Philosophy Development
    • 4.2.3.1 Steps 1 through 9
  • 4.2.4 Generation of TSDs and Test Architecture
    • 4.2.4.1 TSD Transfer Function Values
    • 4.2.4.2 TSD Test/Time Cost Attribute Values
    • 4.2.4.3 TSD Implementation
  • 4.2.5 Test Procedure Development
  • 4.2.6 Board Level Application of DFT Design Tools
    • 4.2.6.1 VHDL Component Modeling
    • 4.2.6.2 Testability Analysis and Interconnection Testing
    • 4.2.6.3 FPGA-Based Board Level ABIST
• 4.3 Technical Summary of Application Example
  • 4.3.1 Tool Application Summary
  • 4.3.2 Reuse Element Listing
  • 4.3.3 Lessons Learned
• 4.4 DFT Economic Analysis
• 4.5 Application Example Conclusions/Summary

5.0 References