module test1;
   wire	o;
   reg	i, enab;
   
   bufif1 #(1:2:3,2,4:5:6) g1 (o, i, enab);

   initial
      begin
	 $monitor ($time, " %b & %b = %b", enab, i, o);
	 #10 {enab, i} = 2'b00; // cut-off buffer
	 #10 {enab, i} = 2'b0x;
	 #10 {enab, i} = 2'b0z;
	 #10 {enab, i} = 2'b01;
	 #10 {enab, i} = 2'b11; // enable buffer; what is the delay?
	 #10 {enab, i} = 2'b10; // fall time
	 #10 {enab, i} = 2'b00; // cut-off
	 #10 {enab, i} = 2'b10; // enable; what is the delay this time?
	 #10 {enab, i} = 2'b1x;
	 #10 {enab, i} = 2'b1z;
	 #30 ;
      end // initial begin

endmodule // test1


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