library IEEE; use IEEE.std_logic_1164.all; entity misr is port ( clock : std_ulogic; reset : std_ulogic; signature_in : in std_ulogic_vector(9 downto 0); signature_out : out std_ulogic_vector(9 downto 0) ); end misr; -- library DFT; architecture modular of misr is signal sig_reg : std_ulogic_vector(9 downto 0); begin process (clock) variable lfsr_tap : std_ulogic; begin if clock'EVENT and clock='1' then if reset = '1' then sig_reg <= (others => '0'); else lfsr_tap := sig_reg(6) xor sig_reg(9); sig_reg(9 downto 1) <= sig_reg(8 downto 0) xor signature_in(9 downto 1); sig_reg(0) <= lfsr_tap xor signature_in(0); end if; end if; end process; signature_out <= sig_reg; end modular;