library IEEE; use IEEE.std_logic_1164.all; entity sisr is port ( serial_in : std_ulogic; clock : std_ulogic; reset : std_ulogic; lfsr_out : out std_ulogic_vector(9 downto 0); signature_out : out std_ulogic_vector(9 downto 0) ); end sisr; library DFT; architecture modular of sisr is use DFT.all; -- signal component maximal_length_lfsr port ( clock : std_ulogic; reset : std_ulogic; data_out : out std_ulogic_vector(9 downto 0) ); end component; component signature_register port ( data_in : std_ulogic; clock : std_ulogic; reset : std_ulogic; data_out : out std_ulogic_vector(9 downto 0) ); end component; begin generator: maximal_length_lfsr port map (clock, reset, lfsr_out); analyzer: signature_register port map (serial_in, clock, reset, signature_out); end modular; <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>