-- -- Rcsid[] = "$Id: regpair.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $"; -- entity regpair is port( Q: out bit_vector(0 to 15); D: in bit_vector(0 to 15); CLEAR,VCC,WRLOW,WRHIGH,WRBOTH,CK: in bit ); end; architecture structure of regpair is component reg_8bit port(Q: out bit_vector(0 to 7); D: in bit_vector(0 to 7); CK, WRENABLE, CLEAR, PRESET: in bit); end component ; signal wrenable0, wrenable1: bit; begin U0 : reg_8bit port map(Q(0 to 7),D(0 to 7),CK,wrenable0,CLEAR,VCC); U1 : reg_8bit port map(Q(8 to 15),D(8 to 15),CK,wrenable1,CLEAR,VCC); U2 : or_gate generic map(1,1) port map(wrenable0,WRLOW,WRBOTH); U3 : or_gate generic map(1,1) port map(wrenable1,WRHIGH,WRBOTH); end structure; <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>