--
-- Rcsid[] = "$Id: reg_ctrl.vhd,v 2.1 1993/10/06 01:04:36 alex Exp $";
--
---------------------------------------------
-- reg_ctrl.vhd
-- June 19, 1993
---------------------------------------------
entity reg_ctrl is
port(WRPC,LOADLATCH,INCRLATCH,PCOUT,
PCHOUT,PCLOUT,WRPCL,WRPCH,DECRLATCH,
SEL16BUS,SEL_CNTR,SPOUT,
ENLATCHOUT,HOUT,LOUT,WRL,WRH,WRB,
WRC,WRD,WRE,WRSP0,WRSP1,BOUT,COUT,
DOUT,EOUT,SP0OUT,SP1OUT,WRAUXACC,
WRSP,WRBC,WRHL,WRDE,HLOUT,
BCOUT,DEOUT,WR2TEMP,ACCOUT,WRACC,
ALUOUT,LOADZ,LOADW,ENWZOUT,WRWZ,WRAUXACC1,TEMP_OUT: out bit;
I5,I4,I3,I2,I1,I0,
VCC,GND,
M1,M2,M3,M4,M5,T1,T2,T3,T4,T5,T6,
CC6,LASTMC,INA,CC,CCBAR,MDROUT: in bit;
ID: in bit_vector(0 to 19));
end;
architecture structure of reg_ctrl is
component pc_cntrl
port(WRPC,LOADLATCH,INCRLATCH,PCOUT,LOADMAR,CALL,PCHOUT,PCLOUT,
WRPCL,WRPCH,LOADZ,LOADW,ENWZOUT,WRWZINLATCH: out bit;
ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,
ID13,ID16,ID19,I3,I5,M1,M2,M3,M4,M5,T2,T3,T4,T6,CC6,LASTMC,
RETURNBAR,CCBAR,INA,T1,LHLD: in bit);
end component;
component sp_cntrl
port(INCRLATCH,DECRLATCH,SPOUT,LOADLATCH,RETRN: out bit;
ID0,ID1,ID4,ID5,ID7,ID9,ID19,CALL,XTHL,CCBAR,
M1,M2,M3,M4,T1,T2,T3,T4,T5,T6,LASTMT,I3: in bit);
end component;
component regctrl0
port(HOUT,LOUT,WRH,WRL,LDLATCHBOTH,ENLATCHOUT,INCRLATCH,XTHL,LHLD,
LOADZ,LOADW,WRWZINLATCH,ENWZOUT: out bit;
ID0,ID1,ID2,ID3,ID4,ID8,ID10,ID11,ID12,ID13,ID14,ID15,ID16,
ID19,M2,M3,M4,M5,T1,T2,T3,I3,LASTMT,CC: in bit);
end component;
component regctrl1
port(DECRLATCH,INCRLATCH,SEL16BUS,WRBC,WRDE,WRHL,WRSP,BCOUT,DEOUT,
HLOUT,SPOUT,BOUT,COUT,DOUT,EOUT,HOUT,LOUT,SP0OUT,SP1OUT,WRB,
WRC,WRD,WRE,WRH,WRL,WRSP0,WRSP1,WRAUXACC,WRAUXACC1,LOADLATCH,
XCHGT4,XCHGT1: out bit;
ID0,ID1,ID2,ID3,ID4,ID5,ID6,ID7,ID8,ID9,ID10,ID11,ID12,ID13,
ID15,ID16,ID18,ID19,I3,I4,I5,M1,M2,M3,M4,
T1,T2,T3,T4,T5,T6,CCBAR,VCC: in bit);
end component;
component regctrl2
port(B_OUT,C_OUT,D_OUT,E_OUT,H_OUT,L_OUT,A_OUT,
WRB,WRC,WRD,WRE,WRH,WRL,WRACC: out bit;
M1,M2,T1,T3,T4,ID4,ID5,ID6,ID14,ID16,ID17,I0,I1,I2,
I3,I4,I5,VCC,GND: in bit);
end component;
component tempctrl
port(HLOUT,WR2TEMP : out bit;
ID1,ID3,ID4,ID5,ID6,ID7,ID12,ID14,
ID16,ID17,ID18,ID19,I3,M1,M2,M3,T2,T3,T4: in bit);
end component;
component acc_ctrl
port(ACCWR, ACCOUTEN: out bit;
ID0, ID1, ID2, ID3, ID5, ID6, ID7, ID8, ID9: in bit;
ID10, ID11, ID12, ID13, ID14, ID15, ID16, ID18, ID19: in bit;
M1, M2, M3, M4, T1, T2, T3, T4: in bit);
end component;
signal LOADLATCH0, INCRLATCH0: bit;
signal SPOUT0, HOUT0, LOUT0, WRH0, WRL0: bit;
signal LOADLATCH2, ENLATCHOUT0, INCRLATCH2: bit;
signal XTHL, LHLD, LOADZ2, LOADW2, WRWZINLATCH2, ENWZOUT2: bit;
signal DECRLATCH1, INCRLATCH3, SEL16BUS0,ACCOUT0, HLOUT1: bit;
signal BOUT1, COUT1,DOUT1, EOUT1, HOUT2, LOUT2: bit;
signal WRB1, WRC1, WRD1, WRE1, WRH2, WRL2, WRACC0: bit;
signal WRWZINLATCH, RIM, LOADW1, LOADZ1, ENWZOUT1, WRWZINLATCH1: bit;
signal INCRLATCH1, DECRLATCH0, LOADLATCH1: bit;
signal HLOUT0, SPOUT1, BOUT0, COUT0, DOUT0, EOUT0, HOUT1, LOUT1, WRB0, WRC0, WRD0, WRE0, WRH1, WRL1: bit;
signal LOADLATCH3, ENWZOUT3, WRACC1, ACCOUT1: bit;
signal CALL, RETRN: bit;
signal LOADMAR_buf, INCRLATCH_buf, DECRLATCH_buf,SEL_CNTR_buf: bit;
signal ACCOUT_buf, SP0OUT_buf, SP1OUT_buf: bit;
signal BOUT_buf, COUT_buf, DOUT_buf, EOUT_buf: bit;
signal HOUT_buf, LOUT_buf, PCLOUT_buf, PCHOUT_buf: bit;
signal LOADLATCH_buf, TEMP_OUT_buf: bit;
signal POP,n100,GATE_16BUS: bit;
signal WRB_buf, WRD_buf, WRH_buf: bit;
signal WRWZ1, WRWZ2: bit;
begin
PCC : PC_CNTRL port map(WRPC,LOADLATCH0,INCRLATCH0,PCOUT,LOADMAR_buf,CALL,
PCHOUT_buf,PCLOUT_buf,WRPCL,WRPCH,LOADZ1,LOADW1,
ENWZOUT1,WRWZINLATCH1,ID(0 to 11),ID(13),ID(16),ID(19),
I3,I5,M1,M2,M3,M4,M5,T2,T3,T4,T6,CC6,LASTMC,RETRN,CCBAR,INA,T1,LHLD);
SPC : SP_CNTRL port map(INCRLATCH1,DECRLATCH0,SPOUT0,LOADLATCH1,RETRN,ID(0),
ID(1),ID(4),ID(5),ID(7),ID(9),ID(19),CALL,XTHL,CCBAR,M1,M2,
M3,M4,T1,T2,T3,T4,T5,T6,LOADMAR_buf,I3);
RC0 : REGCTRL0 port map(HOUT0,LOUT0,WRH0,WRL0,LOADLATCH2,ENLATCHOUT0,
INCRLATCH2,XTHL,LHLD,LOADZ2,LOADW2,WRWZINLATCH2,ENWZOUT2,
ID(0 to 4),ID(8),ID(10 to 16),ID(19),M2,M3,M4,M5,
T1,T2,T3,I3,LOADMAR_buf,CC);
-- LOADMAR signal is high in the last T state of the last machine
-- cycle of the instruction
RC1 : REGCTRL1 port map(DECRLATCH1,INCRLATCH3,SEL16BUS0,WRBC,WRDE,WRHL,
WRSP,BCOUT,DEOUT,HLOUT0,SPOUT1,BOUT0,COUT0,DOUT0,EOUT0,
HOUT1,LOUT1,SP0OUT_buf,SP1OUT_buf,WRB0,WRC0,WRD0,
WRE0,WRH1,WRL1,WRSP0,WRSP1,WRAUXACC,WRAUXACC1,
LOADLATCH3,WRWZ1,ENWZOUT3,ID(0 to 13),ID(15 to 16),
ID(18 to 19),I3,I4,I5,M1,M2,M3,M4,T1,T2,T3,T4,T5,T6,CCBAR,VCC);
RC2 : REGCTRL2 port map(BOUT1,COUT1,DOUT1,EOUT1,HOUT2,LOUT2,ACCOUT0,
WRB1,WRC1,WRD1,WRE1,WRH2,WRL2,WRACC0,
M1,M2,T1,T3,T4,ID(4 to 6),ID(14),ID(16 to 17),
I0,I1,I2,I3,I4,I5,VCC,GND);
TC : TEMPCTRL port map(HLOUT1,WR2TEMP,ID(1),ID(3 to 7),
ID(12),ID(14),ID(16 to 19),I3,M1,M2,M3,T2,T3,T4);
ACC : ACC_CTRL port map(WRACC1,ACCOUT1,ID(0 to 3),ID(5 to 16),
ID(18 to 19),M1,M2,M3,M4,T1,T2,T3,T4);
U8 : or_gate generic map (1,1) port map(INCRLATCH_buf,INCRLATCH0,INCRLATCH1,INCRLATCH2,INCRLATCH3);
U9 : or_gate generic map (1,1) port map(LOADLATCH_buf,LOADLATCH0,LOADLATCH1,LOADLATCH2,LOADLATCH3,WRWZINLATCH);
U10a : or_gate generic map (1,1) port map(SEL_CNTR_buf,INCRLATCH_buf,LOADLATCH_buf,DECRLATCH_buf,SEL16BUS0,ENLATCHOUT0);
U10b : buf_gate port map(SEL_CNTR,SEL_CNTR_buf);
U10x : and_gate port map(SEL16BUS,SEL_CNTR_buf,GATE_16BUS);
U11 : or_gate generic map (1,1) port map(ENLATCHOUT,INCRLATCH_buf,DECRLATCH_buf,ENLATCHOUT0);
U12 : or_gate generic map (1,1) port map(DECRLATCH_buf,DECRLATCH0,DECRLATCH1);
U13 : or_gate generic map (1,1) port map(HOUT_buf,HOUT0,HOUT1,HOUT2);
U14 : or_gate generic map (1,1) port map(LOUT_buf,LOUT0,LOUT1,LOUT2);
U15 : or_gate generic map (1,1) port map(WRH_buf,WRH0,WRH1,WRH2);
U16 : or_gate generic map (1,1) port map(WRL,WRL0,WRL1,WRL2);
U17 : or_gate generic map (1,1) port map(SPOUT,SPOUT0,SPOUT1);
U18 : or_gate generic map (1,1) port map(BOUT_buf,BOUT0,BOUT1);
U19 : or_gate generic map (1,1) port map(COUT_buf,COUT0,COUT1);
U20 : or_gate generic map (1,1) port map(DOUT_buf,DOUT0,DOUT1);
U21 : or_gate generic map (1,1) port map(EOUT_buf,EOUT0,EOUT1);
U22 : or_gate generic map (1,1) port map(WRB_buf,WRB0,WRB1);
U23 : or_gate generic map (1,1) port map(WRC,WRC0,WRC1);
U24 : or_gate generic map (1,1) port map(WRD_buf,WRD0,WRD1);
U25 : or_gate generic map (1,1) port map(WRE,WRE0,WRE1);
U26 : or_gate generic map (1,1) port map(HLOUT,HLOUT0,HLOUT1,LOADLATCH0); -- takes care of
-- PCHL instruction too
U27 : or_gate generic map (1,1) port map(ACCOUT_buf,ACCOUT0,ACCOUT1);
U28 : or_gate generic map (1,1) port map(WRACC,WRACC0,WRACC1);
--U29 : nor_gate generic map (1,1) port map(PUSHPSW,ID(19),ID(14),ID(5),M3,T2);
U30 : nor_gate generic map (1,1) port map(RIM,ID(16),ID(12),ID(0),T2);
U31 : nor_gate generic map (1,1) port map(ALUOUT,RIM,ACCOUT_buf,SP0OUT_buf,
SP1OUT_buf,BOUT_buf,COUT_buf,DOUT_buf,EOUT_buf,HOUT_buf,LOUT_buf,
MDROUT,PCHOUT_buf,PCLOUT_buf,TEMP_OUT_buf);
U32 : or_gate generic map (1,1) port map(LOADW,LOADW1,LOADW2);
U33 : or_gate generic map (1,1) port map(LOADZ,LOADZ1,LOADZ2);
U34 : or_gate generic map (1,1) port map(ENWZOUT,ENWZOUT1,ENWZOUT2,ENWZOUT3);
U35 : or_gate generic map (1,1) port map(WRWZINLATCH,WRWZINLATCH1,WRWZINLATCH2);
buf2 : buf8 port map(INCRLATCH,DECRLATCH,ACCOUT,SP0OUT,SP1OUT,BOUT,COUT,DOUT,
INCRLATCH_buf,DECRLATCH_buf,ACCOUT_buf,SP0OUT_buf,
SP1OUT_buf,BOUT_buf,COUT_buf,DOUT_buf);
buf10 : buf8 port map(EOUT,HOUT,LOUT,PCHOUT,PCLOUT,LOADLATCH,WRB,WRD,
EOUT_buf,HOUT_buf,LOUT_buf,PCHOUT_buf,PCLOUT_buf,
LOADLATCH_buf,WRB_buf,WRD_buf);
-- Gate the loadlatch: during POP, stack pointer gets both halves of DN bus
-- B and C are both loaded from low half of DN bus
-- if(POP) and (WRB or WRD or WRH) then GATE_16BUS := 0;
-- else GATE_16BUS := loadlatch; end if;
U101 : or_gate port map (n100,WRB_buf,WRD_buf,WRH_buf);
U102 : inv_gate port map (POP,ID(19));
U1022 : nand_gate port map(GATE_16BUS,n100,POP);
U105 : buf_gate port map(WRH,WRH_buf);
U200 : NOR_gate generic map(1,1,0,0,0) port map (TEMP_OUT_buf,M2,T2,ID(17),ID(14)); -- MOV M,r
U201 : buf_gate port map(TEMP_OUT,TEMP_OUT_buf);
U210 : OR_gate port map(WRWZ,WRWZ1,WRWZ2);
U211 : NOR_gate port map(WRWZ2,ID(19),ID(7),M3,T2); -- RST i
end structure;
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