Design Analyzer (TM)
DC Professional (TM)
DC Expert (TM)
FPGA Compiler (TM)
VHDL Compiler (TM)
HDL Compiler (TM)
Library Compiler (TM)
Test Compiler (TM)
Version v3.1a -- Mar 16, 1994
Copyright (c) 1988-1994 by Synopsys, Inc.
ALL RIGHTS RESERVED
design_analyzer> read -format vhdl images.vhd
Loading db file '/local/tech15/synopsys/libraries/syn/standard.sldb'
Loading db file '/local/tech15/synopsys/libraries/syn/gtech.db'
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/images.vhd'
Reading in the Synopsys vhdl primitives.
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/images.vhd:
Information: Saving the package 'images'. (HDL-202)
Error: Subprogram body or architecture for 'image' was not defined . (HDL-85)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/images.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl images-body.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/images-body.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/images-body.vhd:
Warning: Alias declarations are not supported for synthesis. They are ignored on line 45 (VHDL-2041)
Error: Object bv_norm not found on line 51 (VHDL-2234)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/images-body.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl bv_arithmetic.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/bv_arithmetic.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/bv_arithmetic.vhd:
Information: Saving the package 'bv_arithmetic'. (HDL-202)
Error: Subprogram body or architecture for 'bv_to_natural' was not defined . (HDL-85)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/bv_arithmetic.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl bv_arithmetic-body.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/bv_arithmetic-body.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/bv_arithmetic-body.vhd:
Warning: Initial values for signals are not supported for synthesis. They are ignored on line 53 (VHDL-2022)
Error: Attribute with arguments 'POS is not supported for synthesis on line 0 (VHDL-2151)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/bv_arithmetic-body.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl syn_bv_arithmetic.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/syn_bv_arithmetic.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/syn_bv_arithmetic.vhd:
Warning: Initial values for signals are not supported for synthesis. They are ignored on line 291 (VHDL-2022)
Error: Attribute with arguments 'POS is not supported for synthesis on line 0 (VHDL-2151)
No designs were read
{}
design_analyzer> read -format vhdl dlx.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx.vhd:
Error: Can't find the package 'MEM_TYPES'
in the library 'DEFAULT'. (LBR-1)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl mem_types.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/mem_types.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/mem_types.vhd:
Information: Saving the package 'mem_types'. (HDL-202)
No designs were read
{}
design_analyzer> read -format vhdl mem_types-body.vhd
Error: Cannot read file 'mem_types-body.vhd'. (UID-58)
No designs were read
{}
design_analyzer> read -format vhdl alu_types.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/alu_types.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/alu_types.vhd:
Information: Saving the package 'alu_types'. (HDL-202)
No designs were read
{}
design_analyzer> read -format vhdl dlx_types.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_types.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_types.vhd:
Information: Saving the package 'dlx_types'. (HDL-202)
Error: Subprogram body or architecture for 'resolve_dlx_word' was not defined . (HDL-85)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_types.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl dlx_rtl.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_rtl.vhd'
**Error: /tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_rtl.vhd line -39
Intermediate file "DEFAULT.MEM_TYPES.sim" has changed. Re-analyze files that depend on this file. (VSS-89)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_rtl.vhd'. (UID-59)
No designs were read
{}
design_analyzer> read -format vhdl dlx_types-body.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_types-body.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx_types-body.vhd:
Warning: Initial values for signals are not supported for synthesis. They are ignored on line 36 (VHDL-2022)
Information: Saving the package 'dlx_types'. (HDL-202)
No designs were read
{}
design_analyzer> read -format vhdl dlx.vhd
Loading vhdl file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx.vhd'
/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx.vhd:
Warning: Type of the generic is assumed to be 'Integer' in synthesis on line 36 (VHDL-2023)
Error: Physical types are not supported for synthesis on line 36 (VHDL-2153)
Error: Can't read 'vhdl' file '/tmp_mnt/users/tech8/hendrich/vhdl/dlx/dlx.vhd'. (UID-59)
No designs were read
{}
design_analyzer>
Thank you...
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