-------------------------------------------------------------------------------- NeoCAD TRACE, Version Foundry 7.0 Copyright 1991-1995 by NeoCAD Inc. All rights reserved. Design file: 5_35.ncd Preference file: filt.prf Device,speed: att2c04,3 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- Preference: FREQUENCY NET "CLK_int" 85.000000 MHz ; 718 items scored, 11 timing errors detected. -------------------------------------------------------------------------------- Error: 9.228ns delay FILT0_A1/ACCLO to FILT0_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.464ns R/F Delay Site Resource R 1.700ns DF.CLK to DF.Q2 FILT0_A1/ACCLO (from CLK_int) R 3.128ns DF.Q2 to DF.A1 FILT0_ZBUS<2> R 4.000ns DF.A1 to DF.COUT FILT0_A1/ACCLO R 0.400ns DF.COUT to CF.CIN FILT0_A1/$SIGNAL_12 (to CLK_int) -------- 9.228ns (61.8% logic, 38.2% route), 2 logic levels. Error: 9.223ns delay FILT4_A1/ACCLO to FILT4_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.459ns R/F Delay Site Resource R 1.700ns FD.CLK to FD.Q1 FILT4_A1/ACCLO (from CLK_int) R 3.123ns FD.Q1 to FD.A0 FILT4_ZBUS<1> R 4.000ns FD.A0 to FD.COUT FILT4_A1/ACCLO R 0.400ns FD.COUT to ED.CIN FILT4_A1/$SIGNAL_12 (to CLK_int) -------- 9.223ns (61.8% logic, 38.2% route), 2 logic levels. Error: 9.212ns delay FILT0_A1/ACCLO to FILT0_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.448ns R/F Delay Site Resource R 1.700ns DF.CLK to DF.Q1 FILT0_A1/ACCLO (from CLK_int) R 3.112ns DF.Q1 to DF.A0 FILT0_ZBUS<1> R 4.000ns DF.A0 to DF.COUT FILT0_A1/ACCLO R 0.400ns DF.COUT to CF.CIN FILT0_A1/$SIGNAL_12 (to CLK_int) -------- 9.212ns (61.9% logic, 38.1% route), 2 logic levels. Error: 9.172ns delay FILT3_A1/ACCLO to FILT3_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.408ns R/F Delay Site Resource R 1.700ns FG.CLK to FG.Q3 FILT3_A1/ACCLO (from CLK_int) R 3.072ns FG.Q3 to FG.A2 FILT3_ZBUS<3> R 4.000ns FG.A2 to FG.COUT FILT3_A1/ACCLO R 0.400ns FG.COUT to EG.CIN FILT3_A1/$SIGNAL_12 (to CLK_int) -------- 9.172ns (62.1% logic, 37.9% route), 2 logic levels. Error: 9.158ns delay FILT4_A1/ACCLO to FILT4_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.394ns R/F Delay Site Resource R 1.700ns FD.CLK to FD.Q2 FILT4_A1/ACCLO (from CLK_int) R 3.058ns FD.Q2 to FD.A1 FILT4_ZBUS<2> R 4.000ns FD.A1 to FD.COUT FILT4_A1/ACCLO R 0.400ns FD.COUT to ED.CIN FILT4_A1/$SIGNAL_12 (to CLK_int) -------- 9.158ns (62.2% logic, 37.8% route), 2 logic levels. Error: 11.780ns delay SEL3 to LAT_BUS<4> exceeds 11.764ns delay constraint less 0.200ns setup requirement (totaling 11.564ns) by 0.216ns R/F Delay Site Resource R 1.700ns HG.CLK to HG.Q1 SEL3 (from CLK_int) R 5.166ns HG.Q1 to TRI.EI.0.T SEL5 R 1.300ns TRI.EI.0.T to TRI.EI.0.O BUFT_INT_BUS<4>_54 R 3.614ns TRI.EI.0.O to EH.WD0 INT_BUS<4> (to CLK_int) -------- 11.780ns (25.5% logic, 74.5% route), 2 logic levels. Error: 8.915ns delay FILT0_A1/ACCHI to FILT0_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.151ns R/F Delay Site Resource R 1.700ns CF.CLK to CF.Q0 FILT0_A1/ACCHI (from CLK_int) R 2.815ns CF.Q0 to DF.A3 FILT0_ZBUS<4> R 4.000ns DF.A3 to DF.COUT FILT0_A1/ACCLO R 0.400ns DF.COUT to CF.CIN FILT0_A1/$SIGNAL_12 (to CLK_int) -------- 8.915ns (63.9% logic, 36.1% route), 2 logic levels. Error: 11.659ns delay SEL3 to LAT_BUS<4> exceeds 11.764ns delay constraint less 0.200ns setup requirement (totaling 11.564ns) by 0.095ns R/F Delay Site Resource R 1.700ns HG.CLK to HG.Q1 SEL3 (from CLK_int) R 5.166ns HG.Q1 to TRI.EI.2.T SEL5 R 1.300ns TRI.EI.2.T to TRI.EI.2.O BUFT_INT_BUS<5>_48 R 3.493ns TRI.EI.2.O to EH.WD1 INT_BUS<5> (to CLK_int) -------- 11.659ns (25.7% logic, 74.3% route), 2 logic levels. Error: 8.797ns delay FILT2_DBUS<0> to FILT2_A1/ACCHI exceeds 11.764ns delay constraint less 3.000ns setup requirement (totaling 8.764ns) by 0.033ns R/F Delay Site Resource R 1.700ns DJ.CLK to DJ.Q3 FILT2_DBUS<0> (from CLK_int) R 2.697ns DJ.Q3 to FJ.B3 FILT2_DBUS<3> R 4.000ns FJ.B3 to FJ.COUT FILT2_A1/ACCLO R 0.400ns FJ.COUT to EJ.CIN FILT2_A1/$SIGNAL_12 (to CLK_int) -------- 8.797ns (64.8% logic, 35.2% route), 2 logic levels. Error: 11.583ns delay SEL0 to LAT_BUS<4> exceeds 11.764ns delay constraint less 0.200ns setup requirement (totaling 11.564ns) by 0.019ns R/F Delay Site Resource R 1.700ns HD.CLK to HD.Q1 SEL0 (from CLK_int) R 4.691ns HD.Q1 to TRI.EA.3.T SEL1 R 1.300ns TRI.EA.3.T to TRI.EA.3.O BUFT_INT_BUS<7>_40 R 3.892ns TRI.EA.3.O to EH.WD3 INT_BUS<7> (to CLK_int) -------- 11.583ns (25.9% logic, 74.1% route), 2 logic levels. Warning: 81.780MHz is the maximum frequency for this preference. 1 preference not met. Timing summary: --------------- Timing errors: 11 Score: 2700 Constraints cover 718 paths, 0 nets, and 802 connections (86.7% coverage) Created Mon Jul 10 09:29:05 1995 --------------------------------------------------------------------------------