-- -----------------------------------------------------------------------------
-- EPM7128SLC84 - TOP LEVEL ENTITY frame design for our FPGA-Praktikum --
-- -----------------------------------------------------------------------------
--
-- File : 'epm7128slc84.vhd'
-- Author : Lars Larsson
--
-- Date : January 4, 1999
--
-- Description : This is a design frame - the top level design for synthesis -
-- for your own designs provided for the in-system programmable
-- Altera EPM7128SLC-15 EPLD. The data sheet of this EPLD is
-- available worldwide under http://www.altera.com/ and locally
-- (domain informatik.uni.hamburg.de) under http://tech-www/00sheets/
--
-- Hint : You MUST NOT change anything within this design frame. Use the
-- ACF file 'epm7128slc84.acf' while synthesis with MAX+plusII !
--
-- -----------------------------------------------------------------------------
--
-- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science
-- University of Hamburg
-- Vogt-Koelln-Str. 30
-- D - 22041 Hamburg, Germany
-- larsson@informatik.uni-hamburg.de
-- http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
--
-- -----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.components.all; -- COMPONENT DEFINITIONS
use work.chips.all; -- CHIPS DEFINITIONS
entity epm7128slc84 is
port(
clk : in std_ulogic; -- clock = 16 MHz [16 MHz quartz oscillator]
nrst : in std_ulogic; -- *reset [automatic power-on reset]
baud_rate_select : in std_ulogic_vector (2 downto 0); -- baud rate selection [DIP-Switch 1]
nsend_receive : in std_ulogic; -- send/receive selection (0:send,1:receive) [DIP-Switches 2-3-4]
rs232_txd : in std_ulogic; -- TXD signal (TTL) from RS232 [from pin 2 of 9]
rs232_rxd : out std_ulogic; -- RXD signal (TTL) to RS232 [to pin 3 of 9]
irda_rxda : in std_ulogic; -- RXD-A (IrDA 1.0) signal from HSDL-1100 [from pin 8]
irda_txd : out std_ulogic; -- TXD (IrDA 1.0 & 1.1) signal to HSDL-1100 [via RC to HSDL-1100 pin TX(7)]
nkey : in std_ulogic; -- strobe key (push down = '0', up = '1') [key beside the DIP-SWITCH]
dip_switches : in std_ulogic_vector (7 downto 0); -- [DIP-Switches 1-2-3-4-5-6-7-8]
--
data : inout std_logic_vector (7 downto 0); -- bidirectional data bits (2Kx8 SRAM, 4Mx8 DRAM)
address : out std_ulogic_vector (10 downto 0); -- address bits A10 downto A0 of SRAM xOR DRAM
nwe : out std_ulogic; -- read / write selector for RAM (not write enable)
--
ncs : out std_ulogic; -- not Chip Select of SRAM]
--
nras : out std_ulogic; -- not Row Address Strobe (nRAS) of DRAM
ncas : out std_ulogic -- not Column Address Strobe (nCAS) of DRAM
);
end epm7128slc84;
architecture structure of epm7128slc84 is
-- SIGNAL DEFINITIONS HERE ---------------------------------------------------------------------------------
signal ram : ram_type; -- RAM type selection RAM <= {SRAM,DRAM}
signal clk_s, nrst_s : std_ulogic; -- clock and reset signal
signal rs232_txd_s, rs232_rxd_s : std_ulogic; -- RS232 signals
signal irda_rxda_s, irda_txd_s : std_ulogic; -- IrDA signals
signal nsend_receive_s : std_ulogic; -- nsend_receive selection signal
signal baud_rate_select_s : std_ulogic_vector (2 downto 0); -- baud rate selection signals
signal dip_switches_s : std_ulogic_vector ( 7 downto 0); -- 8 x DIP switch (blue)
signal nkey_s : std_ulogic; -- strobe key (red)
signal idata_s, odata_s : std_ulogic_vector ( 7 downto 0); -- RAM data bus RAM->idata, odata->RAM
signal address_s : std_ulogic_vector (10 downto 0); -- address bus
signal nwe_s : std_ulogic; -- write enable signal for SRAM & DRAM
signal ncs_s : std_ulogic; -- SRAM chip select signal
signal nras_s : std_ulogic; -- DRAM row address stobe signal
signal ncas_s : std_ulogic; -- DRAM column address strobe signal
-- ---------------------------------------------------------------------------------------------------------
begin
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- connection of TriState port of the EPM7128SLC84 EPLD to signals within this architecture ---------
nwe <= nwe_s;
tristate_p: process ( nwe_s, odata_s )
begin
if (nwe_s='0') then -- write to RAM (drive data)
data <= To_StdLogicVector(odata_s);
else -- read from RAM (read data)
data <= (others=>'Z');
end if;
end process;
idata_s <= To_StdULogicVector(data); -- read data driven from RAM
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- RAM type selection process -----------------------------------------------------------------------
ram_type_p: process( ram, ncs_s, nras_s, ncas_s )
begin
case ram is
when DRAM => ncs<= '1'; nras<= nras_s; ncas<=ncas_s;
when SRAM => ncs<=ncs_s; nras<= '1'; ncas<= '1';
when others => ncs<=ncs_s; nras<= '1'; ncas<= '1';
end case;
end process;
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- ASSOCIATION OF INTERNAL SIGNALS (<signal name>_s) TO THE PORT OF THE ENTITY 'emp7128slc84' --
clk_s <= clk; nrst_s <= nrst;
nsend_receive_s <= nsend_receive; baud_rate_select_s <= baud_rate_select; -- DIP-SWITCHES 1-2-3-4
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- connection of port INPUTS of the EPM7128SLC84 EPLD to signals within this architecture -----------
rs232_txd_s <= rs232_txd;
irda_rxda_s <= irda_rxda;
nkey_s <= nkey;
dip_switches_s <= dip_switches;
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- connection of port OUTPUTS of the EPM7128SLC84 EPLD to signals within this architecture ----------
rs232_rxd <= rs232_rxd_s;
irda_txd <= irda_txd_s;
address <= address_s;
-----------------------------------------------------------------------------------------------------
-- PORT MAP -----------------------------------------------------------------------------------------
epld_p : epld port map (
clk => clk_s, nrst => nrst_s,
baud_rate_select => baud_rate_select_s,
nsend_receive => nsend_receive_s,
rs232_txd => rs232_txd_s, rs232_rxd => rs232_rxd_s,
irda_rxda => irda_rxda_s, irda_txd => irda_txd_s,
nkey => nkey_s, dip_switches => dip_switches_s,
idata => idata_s,
odata => odata_s,
address => address_s,
nwe => nwe_s,
ncs => ncs_s,
nras => nras_s, ncas => ncas_s,
type_of_ram => ram
);
end structure;
-- ---------------------------------------------------------------------------------------------------------
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