-- --------------------------------------------------------------------------- -- SRAM 61256 (32Kx8) - Simplified behavioral SRAM -- -- --------------------------------------------------------------------------- -- -- File : 'sram61256.vhd' -- Author : Lars Larsson -- -- Date : February 15, 1999 -- -- Description : This is a very simple SRAM (32Kx8) model without timing. -- It was just used for data storage in a system simulation -- environment. It's size and pinning is similar to 61256 -- (MSM52256, ...) SRAMs. -- -- ----------------------------------------------------------------------------- -- -- Copyright (C) 1999 Lars Larsson, Dept. of Computer Science -- University of Hamburg -- Vogt-Koelln-Str. 30 -- D - 22041 Hamburg, Germany -- larsson@informatik.uni-hamburg.de -- http://tech-www.informatik.uni-hamburg.de/~larsson -- -- This program is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at your -- option) any later version. -- -- This program is distributed in the hope that it will be useful, but -- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- -- You should have received a copy of the GNU General Public License along -- with this program; if not, write to the Free Software Foundation, Inc., -- 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -- -- ----------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity sram61256 is port( nwe : in std_logic; -- Not Write Enable ncs : in std_logic; -- Not Chip Select noe : in std_logic; -- Not Output Enable address : in std_logic_vector (14 downto 0); -- ADDRESS bus data : inout std_logic_vector ( 7 downto 0) -- bidirectional DATA bus ); end sram61256; architecture behavior of sram61256 is type memory is array ( integer range 0 to 32767 ) of std_logic_vector (7 downto 0); signal idata_s, odata_s : std_logic_vector (7 downto 0); begin tristate_p : process ( odata_s, nwe, noe ) begin if (nwe='1') then if (noe='0') then data <= odata_s; else data <= (others=>'Z'); end if; else data <= (others=>'Z'); end if; end process; idata_s <= data; ram_p : process( nwe, ncs, address, idata_s ) variable sram : memory; begin if (nwe='0') then if (ncs='0') then sram(conv_integer(address)) := idata_s; end if; else if (ncs='0') then odata_s <= sram(conv_integer(address)); else odata_s <= (others=>'Z'); end if; end if; end process; end behavior; -- -----------------------------------------------------------------------------