-- ---------------------------------------------------------------------------
--  IrDA Fuse TEST BENCH for 'irdafuse.vhd'                   -- TEST BENCH --
-- ---------------------------------------------------------------------------
--
--  File   : 'irdafuse_tb.vhd'    
--  Author :  Lars Larsson
--
--  Date   :  November 24, 1998
-- 
--
--  Hints  :  Files 'components.vhd' (package components) and 'simulation.vhd'
--            (package simulation) are required. Simulation should run over 
--            10,000,000 ns
--
-- ---------------------------------------------------------------------------
--
-- Copyright (C) 1998 Lars Larsson, Dept. of Computer Science
--                                  University of Hamburg
--                                  Vogt-Koelln-Str. 30
--                                  D - 22041 Hamburg, Germany
--                                  larsson@informatik.uni-hamburg.de
--                                  http://tech-www.informatik.uni-hamburg.de/~larsson
--
-- This program is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at your
-- option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
--
-- ---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

use work.simulation.all;
use work.components.all;

entity irdafuse_testbench is
end irdafuse_testbench;

architecture simulate of irdafuse_testbench is

 type helper_type is (be_cool, say_ouch);

 signal clk_s, nrst_s, txdin_s, txdout_s, alive_s, killed_s, revival_s : std_ulogic;

 signal helper_s : helper_type;

 begin
  
    clk_p: process 
           begin
             clk_s <= '1'; wait for CLK_PERIOD / 2;
             clk_s <= '0'; wait for CLK_PERIOD / 2;
           end process;
         
    -- rst_p: process
    --        begin 
    --          nrst_s <= '0'; wait for CLK_PERIOD;
    --          nrst_s <= '1'; wait;
    --        end process;
         
    sim_p: process
           begin
 
             revival_s <= '1';  -- self unlock fuse

              nrst_s <= '0'; wait for CLK_PERIOD;

             txdin_s <= '1'; helper_s <=  be_cool;                wait for  25 us;

              nrst_s <= '1';                                      wait for  25 us;  
              nrst_s <= '0'; helper_s <=  be_cool;                wait for 200 us;  
              nrst_s <= '1';                                      wait for  25 us;  

             txdin_s <= '1'; helper_s <=  be_cool;                wait for 100 us;

             txdin_s <= '0'; helper_s <=  be_cool;                wait for 100 us;

             txdin_s <= '1'; helper_s <= say_ouch after T_LIMIT;  wait for 100 us;    

             txdin_s <= '0'; helper_s <=  be_cool after T_RELAX;  wait for 400 us;

             for i in 0 to 10 loop
                 txdin_s <= '1'; wait for 1 us;  -- duty cycle 1:4
                 txdin_s <= '0'; wait for 3 us;
             end loop;

             txdin_s <= '0'; wait for 400 us;

             helper_s <= say_ouch after 3 * T_LIMIT * 2;

             for i in 0 to 400 loop              -- duty cycle 1:3 => lock fuse
                 txdin_s <= '1'; wait for 1 us;
                 txdin_s <= '0'; wait for 2 us;
             end loop;

             txdin_s <= '0'; helper_s <=  be_cool after T_RELAX;  wait for 400 us;

             for i in 0 to 200 loop              -- duty cycle 3:16
                 txdin_s <= '1'; wait for  3 us;
                 txdin_s <= '0'; wait for 13 us;
	         end loop;

             txdin_s <= '0'; wait for 400 us;
             txdin_s <= '1'; helper_s <= say_ouch after T_LIMIT;  wait for 100 us;
             txdin_s <= '0'; helper_s <=  be_cool after T_RELAX;  wait for 400 us;

             txdin_s <= '0'; wait for 400 us;
             txdin_s <= '1'; helper_s <= say_ouch after T_LIMIT;  wait for 400 us;
             txdin_s <= '0'; helper_s <=  be_cool after T_RELAX;  wait for 400 us;

             wait;
           end process;
           
     irdafuse_i: irdafuse port map ( clk_s, nrst_s, txdin_s, txdout_s, alive_s, killed_s, revival_s );
         
  end simulate;

-- ============================ CONFIGURATION ============================

configuration irdafuse_testbench_cfg of irdafuse_testbench is
for simulate
end for;
end irdafuse_testbench_cfg;

-- ======================== END OF CONFIGURATION =========================

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