Copyright (C) 1988 Intermetrics, Inc. All rights reserved.
Standard VHDL 1076 Support Environment Version 2.0 - 1 September 1989
%VHDSIM-N-SIGTRAN Signal Tracing turned on
NICKEL =0 DIME = X Sel = X Ret = X enable = X change = 0
NICKEL =0 DIME = 0 Sel = X Ret = X enable = X change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = X enable = X change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 1 enable = X change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =1 DIME = 0 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 1 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 1 change = 0
NICKEL =0 DIME = 0 Sel = 1 Ret = 0 enable = 1 change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 1 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 1 Sel = 0 Ret = 0 enable = 0 change = 0
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 1 change = 1
NICKEL =0 DIME = 0 Sel = 1 Ret = 0 enable = 1 change = 1
NICKEL =0 DIME = 0 Sel = 0 Ret = 0 enable = 0 change = 0
%VHDSIM-F-ASSERTV Assertion Violation after 150 ns
at line 8126 in procedure SYS_FINISH at line 8122 in package body <<VERILOG_II>>VERILOG_STD
Simulation Terminated By $FINISH.
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