-----------------------------------------------
-- description du controle du DLX-m en VHDL --
-- version m0.3
-- 4 decembre 1992
-----------------------------------------------
--
-- le chemin de test n'est pas implemente, seuls figurent les connecteurs
-- associes fonc .
-- Dans la simulation fonc doit etre mis a 1 .
entity dlxm_ctl is
port( ck : in bit ; -- horloge externe
gel : in bit ; -- gel externe
rqst : in bit ; -- signal int. ext. du status
excp : in bit ; -- ..... exceptions .....
reset : in bit ; -- signal requete reset ...
ir16 : in bit ; -- ir(16) venant du data_p
nul : in bit ; -- flag ................
codop : in bit_vector(5 downto 0) ; -- ir(31:26) ................
mode : in bit ; -- d_status(0) = mode
m_ins : out bit_vector(27 downto 7) ; -- micro-instruction
byte : out bit ; -- flag byte
ico : out bit ; -- flag ico pour status
rw : out bit ; -- flag acces memoire
fonc : in bit ;
vdd : in bit ;
vss : in bit ) ;
end dlxm_ctl ;
architecture FONCTIONAL of dlxm_ctl is
----------------------------
-- Definition des signaux --
----------------------------
signal m_adr : bit_vector(5 downto 0) ;
signal m_adr_reg : reg_vector(5 downto 0) register ;
signal sh_outrom: bit_vector(27 downto 0) ;
signal outrom : reg_vector(27 downto 0) register ;
signal seq : bit_vector(6 downto 0) ;
signal icodop : bit ;
signal cop1 : bit_vector(3 downto 0) ;
signal cop2 : bit_vector(1 downto 0) ;
signal rer : bit;
-------------------------------
-- Definition des constantes --
-------------------------------
constant x_rs : bit_vector(3 downto 0) := B"0000" ; -- m_ins(27 : 24)
constant x_rt : bit_vector(3 downto 0) := B"0001" ;
constant x_pc : bit_vector(3 downto 0) := B"0100" ;
constant x_ad : bit_vector(3 downto 0) := B"0101" ;
constant x_sr : bit_vector(3 downto 0) := B"0110" ;
constant x_iar : bit_vector(3 downto 0) := B"0111" ;
constant x_c0 : bit_vector(3 downto 0) := B"1000" ;
constant x_cb : bit_vector(3 downto 0) := B"1100" ;
constant x_ch : bit_vector(3 downto 0) := B"1111" ;
constant y_i16 : bit_vector(2 downto 0) := B"000" ; -- m_ins(23 :21)
constant y_i18 : bit_vector(2 downto 0) := B"001" ;
constant y_i28 : bit_vector(2 downto 0) := B"010" ;
constant y_dt : bit_vector(2 downto 0) := B"011" ;
constant y_ad : bit_vector(2 downto 0) := B"100" ;
constant y_c0 : bit_vector(2 downto 0) := B"101" ;
constant y_c4 : bit_vector(2 downto 0) := B"110" ;
constant y_c16 : bit_vector(2 downto 0) := B"111" ;
constant a_sumxy : bit_vector(3 downto 0) := B"0001" ; -- m_ins(20 : 17)
constant a_difxy : bit_vector(3 downto 0) := B"0010" ;
constant a_and : bit_vector(3 downto 0) := B"0100" ;
constant a_or : bit_vector(3 downto 0) := B"0101" ;
constant a_xor : bit_vector(3 downto 0) := B"0110" ;
constant a_sll : bit_vector(3 downto 0) := B"0111" ;
constant a_srl : bit_vector(3 downto 0) := B"1000" ;
constant a_sra : bit_vector(3 downto 0) := B"1001" ;
constant a_seq : bit_vector(3 downto 0) := B"1010" ;
constant a_sne : bit_vector(3 downto 0) := B"1011" ;
constant a_sge : bit_vector(3 downto 0) := B"1100" ;
constant a_sgt : bit_vector(3 downto 0) := B"1101" ;
constant a_sle : bit_vector(3 downto 0) := B"1110" ;
constant a_slt : bit_vector(3 downto 0) := B"1111" ;
constant a_nop : bit_vector(3 downto 0) := B"0000" ;
constant r_no : bit_vector(5 downto 0) := B"000000" ; -- m_ins(16 : 11)
constant r_pc : bit_vector(5 downto 0) := B"000001" ;
constant r_ad : bit_vector(5 downto 0) := B"000010" ;
constant r_iar : bit_vector(5 downto 0) := B"000100" ;
constant r_r31 : bit_vector(5 downto 0) := B"001000" ;
constant r_rd : bit_vector(5 downto 0) := B"010000" ;
constant r_sr : bit_vector(5 downto 0) := B"100000" ;
constant m_no : bit_vector(3 downto 0) := B"0011" ; -- m_ins(10 : 7)
constant m_fetch : bit_vector(3 downto 0) := B"1010" ;
constant m_read_w : bit_vector(3 downto 0) := B"0010" ;
constant m_write_w : bit_vector(3 downto 0) := B"0000" ;
constant m_read_b : bit_vector(3 downto 0) := B"0110" ;
constant m_write_b : bit_vector(3 downto 0) := B"0100" ;
constant s_next : bit_vector(6 downto 0) := B"1000001" ; --m_ins(6 : 0)
constant s_i2s : bit_vector(6 downto 0) := B"1100011" ;
constant s_not_nul : bit_vector(6 downto 0) := B"1100101" ;
constant s_nul : bit_vector(6 downto 0) := B"1100111" ;
constant s_s2i : bit_vector(6 downto 0) := B"1111001" ;
constant s_mem : bit_vector(6 downto 0) := B"1011011" ;
constant s_codop_1 : bit_vector(6 downto 0) := B"0001101" ;
constant s_codop_2 : bit_vector(6 downto 0) := B"0101111" ;
constant s_goto_8 : bit_vector(6 downto 0) := B"0010000" ;
constant s_goto_12 : bit_vector(6 downto 0) := B"0011000" ;
constant s_goto_33 : bit_vector(6 downto 0) := B"1000010" ;
constant s_goto_34 : bit_vector(6 downto 0) := B"1000100" ;
constant s_goto_45 : bit_vector(6 downto 0) := B"1011010" ;
constant s_goto_46 : bit_vector(6 downto 0) := B"1011100" ;
constant s_goto_47 : bit_vector(6 downto 0) := B"1011110" ;
constant s_goto_48 : bit_vector(6 downto 0) := B"1100000" ;
constant s_goto_50 : bit_vector(6 downto 0) := B"1100100" ;
constant s_goto_51 : bit_vector(6 downto 0) := B"1100110" ;
begin
------------------------------------
-- definition de signaux internes --
------------------------------------
rer <= (excp or rqst ); -- interruption
seq(6 downto 0) <= outrom(6 downto 0) when (reset ='0') else
-- outrom(6 downto 0) when (rst='1') and (m_adr_reg=B"100001")else
-- irq
-- outrom(6 downto 0) when (rst='1') and (m_adr_reg(5 downto 1) =B"11001") else
-- pct,sr16l
s_goto_33 ;
-------------------------------------------------------------------
-- Determination de m_adr en fonction du sequenceur outrom (6:0)--
-- fonctionnement du micro-sequenceur -----------------------------
-------------------------------------------------------------------
m_adr(5 downto 4) <= seq(6 downto 5) ;
m_adr(3 downto 0) <= seq(4 downto 1) when seq(0)='0' else
B"000" & rer when seq(3 downto 0)=B"0001" else
B"010" & ir16 when seq(3 downto 0)=B"0011" else
B"000" & not(nul) when seq(3 downto 0)=B"0101" else
B"000" & nul when seq(3 downto 0)=B"0111" else
B"110" & ir16 when seq(3 downto 0)=B"1001" else
B"10" & not(codop(2)) & codop(1) when seq(3 downto 0)=B"1011" else
cop2 & codop(1 downto 0) when seq(3 downto 0)=B"1111" else
cop1 ; -- when seq(3 downto 0)=B"1101" ;--
cop2 <= not (codop(4 downto 3)) when (codop(1)='0' and codop(5)='1')
else codop(4 downto 3) ;
icodop <= '1' when ( codop(5 downto 3)=B"000" and codop(0)='1' ) else
'1' when ( codop(5 downto 0)=B"001011" ) else
'1' when ( codop(5 downto 3)=B"011" and codop(1)='0' ) else
'1' when ( codop(5 downto 3)=B"100" and codop(1 downto 0)=B"10") else
'1' when ( codop(5 downto 3)=B"101" and codop(0)='1' ) else
'1' when ( codop(5 downto 1)=B"11011" ) else
'1' when ( codop(5 downto 2)=B"1111" ) else
'1' when ( codop(5 downto 1)=B"11001" and (mode='1')) else
'0';
cop1 <= B"0111" when (icodop = '1') else -- illegal codop
B"0100" when (codop(5)='0' and codop(2)='0') else -- reg
B"0100" when (codop(5 downto 2)=B"1000") else -- reg
B"0101" when (codop(5)='0' and codop(2)='1') else -- imd
B"0110" when (codop(5 downto 2)=B"1001") else -- imdu
B"0000" when (codop(5 downto 3)=B"101") else -- base
B"0010" when (codop(5 downto 4)=B"11" and codop(2)='1' and codop(0)='0') else
B"0011" when (codop(5 downto 4)=B"11" and codop(2)='1' and codop(0)='1') else
'1' & codop(3) & codop(1 downto 0) ; -- when codop(5 downto 4)=B"11" and codop(2)='0') ; --
-----------------------------------------------------------------------
-- Determination de la micro-instruction m_ins en fonction de m_adr --
-----------------------------------------------------------------------
with m_adr(5 downto 0) select
sh_outrom <= x_rs & y_i16 & a_sumxy & r_ad & m_no & s_mem when B"000000" ,--adr
x_rs & y_c0 & a_sumxy & r_no & m_no & s_nul when B"000010" ,--beqz
x_rs & y_c0 & a_sumxy & r_no & m_no & s_not_nul when B"000011" ,--bnez
x_rt & y_c0 & a_sumxy & r_ad & m_no & s_codop_2 when B"000100" ,--reg
x_c0 & y_i16 & a_sumxy & r_ad & m_no & s_codop_2 when B"000101" ,--imd
x_ch & y_i16 & a_and & r_ad & m_no & s_codop_2 when B"000110" ,--imdu
x_pc & y_c4 & a_difxy & r_pc & m_no & s_goto_33 when B"000111" ,--rpc
x_rs & y_c0 & a_sumxy & r_pc & m_no & s_goto_48 when B"001000" ,--jr
x_pc & y_c0 & a_sumxy & r_r31 & m_no & s_goto_8 when B"001001" ,--jalr
x_c0 & y_c0 & a_sumxy & r_no & m_no & s_s2i when B"001010" ,--s2i
x_c0 & y_c0 & a_sumxy & r_no & m_no & s_i2s when B"001011" ,--i2s
x_pc & y_i28 & a_sumxy & r_pc & m_no & s_goto_48 when B"001100" ,--j
x_pc & y_c0 & a_sumxy & r_r31 & m_no & s_goto_12 when B"001101" ,--jal
x_iar & y_c0 & a_sumxy & r_pc & m_no & s_goto_34 when B"001110" ,--rfe
x_pc & y_c0 & a_sumxy & r_iar & m_no & s_goto_51 when B"001111" ,--trap
x_rs & y_ad & a_sumxy & r_ad & m_no & s_goto_47 when B"010000" ,--add
x_rs & y_ad & a_difxy & r_ad & m_no & s_goto_47 when B"010010" ,--sub
x_rs & y_ad & a_xor & r_rd & m_fetch & s_next when B"010011" ,--lxor
x_rs & y_ad & a_sll & r_rd & m_fetch & s_next when B"010100" ,--sll
x_rs & y_ad & a_srl & r_rd & m_fetch & s_next when B"010101" ,--srl
x_rs & y_ad & a_sra & r_rd & m_fetch & s_next when B"010110" ,--sra
x_ad & y_c16 & a_sll & r_rd & m_fetch & s_next when B"010111" ,--lhi
x_rs & y_ad & a_seq & r_rd & m_fetch & s_next when B"011000" ,--seq
x_rs & y_ad & a_sne & r_rd & m_fetch & s_next when B"011001" ,--sne
x_rs & y_ad & a_sge & r_rd & m_fetch & s_next when B"011010" ,--sge
x_rs & y_ad & a_sle & r_rd & m_fetch & s_next when B"011011" ,--sle
x_rs & y_ad & a_and & r_rd & m_fetch & s_next when B"011100" ,--land
x_rs & y_ad & a_or & r_rd & m_fetch & s_next when B"011101" ,--lor
x_rs & y_ad & a_sgt & r_rd & m_fetch & s_next when B"011110" ,--sgt
x_rs & y_ad & a_slt & r_rd & m_fetch & s_next when B"011111" ,--slt
x_pc & y_c4 & a_sumxy & r_pc & m_no & s_codop_1 when B"100000" ,--init
x_pc & y_c0 & a_sumxy & r_iar & m_no & s_goto_51 when B"100001" ,--irq
x_sr & y_c16 & a_srl & r_sr & m_no & s_goto_48 when B"100010" ,--sr16r
x_c0 & y_c0 & a_sumxy & r_no & m_read_w & s_goto_45 when B"101000" ,--lw
x_c0 & y_c0 & a_sumxy & r_no & m_read_b & s_goto_46 when B"101001" ,--lb
x_rt & y_c0 & a_sumxy & r_no & m_write_w & s_goto_48 when B"101010" ,--sw
x_rt & y_c0 & a_sumxy & r_no & m_write_b & s_goto_48 when B"101011" ,--sb
x_c0 & y_dt & a_sumxy & r_rd & m_fetch & s_next when B"101101" ,--lw2
x_cb & y_dt & a_and & r_rd & m_fetch & s_next when B"101110" ,--lb2
x_c0 & y_ad & a_sumxy & r_rd & m_fetch & s_next when B"101111",--novr
x_c0 & y_c0 & a_sumxy & r_no & m_fetch & s_next when B"110000",--ifetch
x_pc & y_i18 & a_sumxy & r_pc & m_no & s_goto_48 when B"110001",--branch
x_c0 & y_c4 & a_difxy & r_pc & m_no & s_goto_48 when B"110010" ,--pct
x_sr & y_c16 & a_sll & r_sr & m_no & s_goto_50 when B"110011" ,--sr16l
x_rs & y_c0 & a_sumxy & r_iar & m_fetch & s_next when B"110100" ,--i2iar
x_rs & y_c0 & a_sumxy & r_sr & m_fetch & s_next when B"110101" ,--i2sr
x_iar & y_c0 & a_sumxy & r_rd & m_fetch & s_next when B"111100" ,--iar2i
x_sr & y_c0 & a_sumxy & r_rd & m_fetch & s_next when B"111101" ,--sr2i
x_c0 & y_c0 & a_sumxy & r_no & m_no & s_goto_33 when others ;
--------------------------------------------------
-- Stokage de l'adresse de la micro instruction --
--------------------------------------------------
b_madrreg : block ((ck='0') and (gel = '0') and not ck'STABLE)
begin
m_adr_reg(5 downto 0) <= guarded (m_adr(5 downto 0)) ;
end block ;
------------------------------------------
-- Determination de la sortie de la rom --
------------------------------------------
b_outrom : block ((ck='0') and (gel = '0') and not ck'STABLE)
begin
outrom(27 downto 0) <= guarded (sh_outrom(27 downto 0)) ;
end block ;
-------------------------------
-- Determination des sorties --
-------------------------------
--
--------------------------------------------
-- le chemin de test n est pas implemente --
--------------------------------------------
-- champs opx opy alu
m_ins(27 downto 17) <= outrom(27 downto 17) ;
-- champ res
m_ins(16 downto 11) <= outrom(16 downto 11) when (excp='0')
else
outrom(16 downto 11) when ((excp='1')and(m_adr_reg=B"000111")) -- rpc
else
outrom(16 downto 11) when ((excp='1')and(m_adr_reg=B"100001")) -- irq
else
outrom(16 downto 11) when ((excp='1')and(m_adr_reg(5 downto 1) = B"11001")) -- pct ou sr16l
else
B"000000" ; -- champ res = r_no
-- champ acces memoire
m_ins(10 downto 7) <= outrom(10 downto 7) when ( excp ='0')
else
B"0011" ; -- m_no
byte <= outrom(9) ; -- '0' par defaut : word
rw <= outrom(8) ; -- '1' par defaut : read
ico <= icodop when m_adr_reg(5 downto 0) = B"100000" -- init
else
'0' ;
end FONCTIONAL ;
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