"High-Performance Adder Circuit Generators in Parameterized Structural VHDL" H. Kunz and R. Zimmermann Abstract -------- In ASIC design, arithmetic components are usually selected from tool- and technology-dependent libraries providing very limited flexibility and choice of circuit structures. With the possibility of parameterized structural circuit descriptions at the gate-level in VHDL, versatile circuit generators can be implemented which are highly independent of tool platforms and design technologies. This enables the realization of a universal and comprehensive library of efficient arithmetic components in form of a collection of synthesizable VHDL code entities. In a first step, high-performance adder generators were implemented using this method. Additionally, valuable experience was gained with respect to the implementation of circuit generators using parameterized structural VHDL. <div align="center"><br /><script type="text/javascript"><!-- google_ad_client = "pub-7293844627074885"; //468x60, Created at 07. 11. 25 google_ad_slot = "8619794253"; google_ad_width = 468; google_ad_height = 60; //--></script> <script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"> </script><br /> </div>