--
-- sel = '0'   a <- z  input from z to a, z <= 'Z' 
-- sel = '1'   a -> z  ouput from a to z

LIBRARY ieee;  USE ieee.std_logic_1164.all;
USE work.global_signal.all;

ARCHITECTURE spec OF tri_state_vector IS
   ALIAS a_aligned : std_logic_vector(z'range) is a;

BEGIN
   p1 : process (z, a, sel, sys_rst) is
   begin
      for n in z'range loop
         if sys_rst = '1' then
            z(n) <= '0';
         elsif sel = '0' then
            z(n) <= 'Z'; 
         elsif sel = '1' and (a_aligned(n) = '0' 
                              or a_aligned(n) = '1') then
            z(n) <= a_aligned(n); 
         else 
            z(n) <= 'X';
         end if;
      end loop;
   end process p1;
END architecture spec;

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