--
LIBRARY ieee;  USE ieee.std_logic_1164.all;
USE work.global_signal.all;

ARCHITECTURE struct of time_memory is

   COMPONENT reg4 IS
      PORT ( data : INOUT std_logic_vector (3 downto 0);
             enable : IN std_logic );
   END COMPONENT reg4;

   COMPONENT reg3 IS
      PORT ( data : INOUT std_logic_vector (2 downto 0);
             enable : IN std_logic );
   END COMPONENT reg3;

BEGIN
   r1 : COMPONENT reg4
      PORT MAP ( data => time_data (3 downto 0),
                 enable => pause_now );

   r2 : COMPONENT reg4
      PORT MAP ( data => time_data (7 downto 4),
                 enable => pause_now );

   r3 : COMPONENT reg4
      PORT MAP ( data => time_data (11 downto 8),
                 enable => pause_now );

   r4 : COMPONENT reg3
      PORT MAP ( data => time_data (14 downto 12),
                 enable => pause_now );

   r5 : COMPONENT reg4
      PORT MAP ( data => time_data (18 downto 15),
                 enable => pause_now );

   r6 : COMPONENT reg4
      PORT MAP ( data => time_data (22 downto 19),
                 enable => pause_now );

END ARCHITECTURE struct;

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