SDSP Memory Model

   USE WORK.SDSP_types.ALL;

   ENTITY memory IS
     GENERIC (Tpd : TIME := unit_delay);
     PORT (d_bus : INOUT bus_bit_32 bus;
           a_bus : IN bit_32;
           read, write : IN BIT;
           ready : OUT BIT);
   END memory:

   ARCHITECTURE behavior OF memory IS
   BEGIN
     PROCESS
       CONSTANT low_address : integer := 0;
       CONSTANT high_address : integer := 65535;
       TYPE memory_array is
         array (INTEGER RANGE low_address TO high_address) of bit_32;
       VARIABLE mem : memory_array;
       VARIABLE address : INTEGER;

   BEGIN  -- put d_bus and reply into initial state
        d_bus <= NULL AFTER Tpd;
        READY <= '0' AFTER Tpd;
        WAIT UNTIL (read = '1') OR (write = '1');  -- wait for a command
        -- dispatch read or write cycle
        address := bits_to_int(a_bus);
        IF address >= low_address AND address <= high_address THEN
          IF write = '1' THEN -- address match for this memory
             ready <= '1' AFTER Tpd;
             WAIT UNTIL write = '0'; -- end of write cycle
             mem(address) := d_bus'delayed(Tpd);  -- sample data 
          ELSE  -- read = '1'
             d_bus <= mem(address) AFTER Tpd;   -- fetch data
              ready <= '1' AFTER Tpd;
              WAIT UNTIL read ='0';   -- hold for read cycle
          END IF;
       END IF;
     END PROCESSS;
   END behavior;