Sized & Unsized Numbers

In Verilog numbers are declared using the following notation:

The value <size> is the size in bits (not digits) of memory allocated to the number. e.g.

test = 2'd27; // incorrect assignment (warning #1), test = 3 (last 2 bits)
test = 5'd27; // correct assigment, test = 27

If no size is declared or if the number is the output of an expression then Verilog uses a set of rules to size the number.

• If the number is an unsized constant number then the integer bit length is used to store the number (see below).
• If the number is the output of a logical/relational operation (e.g. <, ~&) then a bit length of 1 is used to store the number.
• If the number is the output of a numerical operation (e.g. +, *, ?) the size of the largest operand is used to store the output number (regardless of whether the output is too large).

module test1;

   initial begin
      $display("Binary output");
      $display("--------------------------------");
      
      $display("%b",7); // unsized constant, output bit length=32
      $display("%b",4'd7); // sized constant
      $display("%b",4'd13+2'd3); // output bit length = 4, output incorrect!
      $display("%b",4'd13+5'd3); // output bit length = 5, output correct!
      $display("%b",(4'd13>5'd2)); // output bit length = 1
   end
endmodule // test1

Binary output
--------------------------------
00000000000000000000000000000111
0111
0000
10000
1

If the number is subsequently assigned to a variable then the variable's predefined size is used to store the number and the above rules do not apply.

• Real and Time numbers are assigned 64 bits of memory (this value is machine dependent).
• Integer numbers are assigned 32 bits of memory (this value is machine dependent). The first bit is the sign (0 is positive, 1 is negative). Negative numbers are represented in two's complement form. Fractions are rounded. All arithmetic is executed as expected.

module test2;

   integer test;

   initial $monitor ("%b %d",test,test);
   
   initial begin
      $display("Binary                               Decimal");
      $display("--------------------------------------------");
  
      test=4'd10; // 4 bits assigned for number but integer stored in 32 bits
      #10;
      test=test-20; // negative numbers no problem
      #10;
      test='b1000_0000_0000_0000_0000_0000_0000_0000; // largest negative
      #10;
      test='b0111_1111_1111_1111_1111_1111_1111_1111; // largest positive
      #10;
      test=(4'd13+2'd3); // bit length of output is no longer determined by
                         // max bit length of operand
      #10;
      test=2'd27; // incorrect assignment
      #10;
      test=13.7; // decimal points rounded
      #10;
      
      $finish;
   end // initial begin
endmodule // test2

Binary                               Decimal
--------------------------------------------
00000000000000000000000000001010          10
11111111111111111111111111110110         -10
10000000000000000000000000000000 -2147483648
01111111111111111111111111111111  2147483647
00000000000000000000000000010000          16
00000000000000000000000000000011           3
00000000000000000000000000001110          14

• Registers must have a predeclared size on setup. If no size is specified in declaration then a default size of 1 bit is used. If during assignment to an n-bit register the bit length is exceeded the register takes the value of the 'n' least significant bits of the assigned number. Negative numbers cannot be represented by a register so care should be taken when applying arithmetical operations to register.

module test3;

   reg       test;
   reg [3:0] test2;

   initial $monitor ("     %b            %b          %d",test,test2,test2);
   
   initial begin
      $display ("test(binary) test2(binary) test2(decimal)");
      $display ("-----------------------------------------");

      test=4'd7; // incorrect assignment - this does not generate a warning!!
                 // the LSB is assigned to the 1 bit register.
      test2=4'd7; // correct assignment
      #10;
      test2=test2-5; // arithmetic is carried out as expected on positive numbers
      #10;
      test2=test2-3; // registers do not store negative numbers
      #10;
      test2=test2+5; // exceeding the predefined size of the register does not
                     // generate a warning
      #10;
  
      $finish;
   end // initial begin
endmodule // test3

test(binary) test2(binary) test2(decimal)
-----------------------------------------
     1            0111           7
     1            0010           2
     1            1111          15
     1            0100           4

Typical Verilog Warnings

The Verilog compiler will not generate warnings for all sizing errors. Any warnings that are reported will not halt the execution of the program but should be corrected.