System Tasks

Ending a simulation.

Keywords: $stop, $finish.

$finish exits the simulation and passes control to the operating system. $stop suspend the simulation and puts Verilog into interative mode. See example below.

        initial begin
          clock = 1'b0;
          ... // whatever you want to be doing
          #200 $stop   // this will suspend the simulation and put it in
                    // interactive mode
          #500 $finish // this will end the simulation alltogether.
        end