Logic Statement Implementation.

Now we implement the same multiplexor as a logic statement.

        module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1, cntrl2);
           output out;
           input in1, in2, in3, in4, cntrl1, cntrl2;

           assign out = (in1 & ~cntrl1 & ~cntrl2) |
                        (in2 & ~cntrl1 &  cntrl2) |
                        (in3 &  cntrl1 & ~cntrl2) |
                        (in4 &  cntrl1 &  cntrl2);
        endmodule

This is a higher level of abstraction than the gate level description, it is still fairly unintelligible, we will see it becoming more and more intelligible as we move up levels of abstractions in the following sections.

        module multiplexor4_1 (out, in1, in2, in3 ,in4, cntrl1, cntrl2);
          output out;
          input in1, in2, in3, in4, cntrl1, cntrl2;

The first few lines must stay the same so any module which is accessing the multiplexor does not have to change, ie. the communication stays the same.

        assign out = (in1 & ~cntrl1 & ~cntrl2) |
                     (in2 & ~cntrl1 &  cntrl2) |
                     (in3 &  cntrl1 & ~cntrl2) |
                     (in4 &  cntrl1 &  cntrl2);
        endmodule

This is a continuous assignment to the wire out. It is reevaluated and assigned to out everytime any of the operands change.

previous next contents