If no parentheses are used to separate operands then Verilog uses the following rules of precedence. It is normally a good idea to use parentheses to make expressions readable. Below is a list of all operators provided by Verilog and their precedence rules.
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| Operator | Operator | Operation | Number of |
| Type | Symbol | | Operands |
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| Arithmetic | * | multiply | two |
| | / | divide | two |
| | + | add | two |
| | - | subtract | two |
| | % | modulus | two |
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| Logical | ! | logical negation | one |
| | && | logical and | two |
| | || | logical or | two |
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| Relational | > | greater than | two |
| | < | less than | two |
| | >= | greater or equal | two |
| | <= | less or equal | two |
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| Equality | == | equality | two |
| | != | inequality | two |
| | === | case equality | two |
| | !== | case inequality | two |
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| Bitwise | ~ | bitwise negation | one |
| | & | bitwise and | two |
| | | | bitwise or | two |
| | ^ | bitwise xor | two |
| | ^~or~^ | bitwise xnor | two |
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| Reduction | & | reduction and | one |
| | ~& | reduction nand | one |
| | | | reduction or | one |
| | ~| | reduction nor | one |
| | ^ | reduction xor | one |
| | ^~or^~ | reduction xnor | one |
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| Shift | >> | right shift | two |
| | << | left shift | two |
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| Concatenation | {} | concatenation | any |
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| Replication | {{}} | replication | any |
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| Conditional | ?: | conditional | three |
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| Operator | Precedence |
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| + - ! ~ (unary) | highest |
| * / % | |
| + - (binary) | |
| << >> | |
| < <= > >= | |
| == != === !== | |
| & ~& | |
| ^ ^~ | |
| | ~| | |
| && | |
| || | |
| ?: (conditional) | lowest |
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