-------------------------------------------------------------------------------
-- Synthesizable examples cover a large set of VHDL synthesizable constructs --
-- All examples have been synthesized with the Exemplar logic Core --
-- Copyright 1995, Zainalabedin Navabi navabi@ece.ut.ac.ir navabi@ece.neu.edu--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--
LIBRARY exemplar;
USE exemplar.exemplar_1164.ALL;
USE exemplar.exemplar.ALL;
ENTITY walking1_counter IS
PORT (clock, reset : IN std_logic;
count_out : INOUT std_logic_vector (7 DOWNTO 0));
END;
ARCHITECTURE dataflow OF walking1_counter IS
BEGIN
walking : BLOCK (NOT clock'STABLE AND clock = '1')
BEGIN
count_out <= GUARDED "10000000" WHEN reset = '1' ELSE
count_out(0) & count_out(7 DOWNTO 1);
END BLOCK;
END dataflow;
--ARCHITECTURE badly_coded OF walking1_counter IS
--BEGIN
---- All shifting happens in one delta, repeats forever ----
-- walking : BLOCK (clock'EVENT AND clock = '1')
-- BEGIN
-- count_out <= GUARDED "10000000" WHEN reset = '1' ELSE
-- count_out(0) & count_out(7 DOWNTO 1);
-- END BLOCK;
--END badly_coded;
<div align="center"><br /><script type="text/javascript"><!--
google_ad_client = "pub-7293844627074885";
//468x60, Created at 07. 11. 25
google_ad_slot = "8619794253";
google_ad_width = 468;
google_ad_height = 60;
//--></script>
<script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js">
</script><br /> </div>