-- -- Program -- D:\EXEMPLAR\BIN\PC\FPGA.EXE D:\EXEMPLAR\TUTORIAL\LOGIC4.VHD D:\EXEMPLAR\TUTO -- RIAL\HARDWARE\LOGIC4.VHD -COMMAND_FILE=D:\EXEMPLAR\DEMO\TMP23.$$$ -- Version V2.1.4 -- Definition of LOGIC4 -- -- VHDL Structural Description, created by -- Exemplar Logic's CORE -- Sat Mar 4 04:55:40 1995 -- -- -- library ieee ; use ieee.std_logic_1164.all ; LIBRARY exemplar; USE exemplar.Cypress_pASIC.ALL; entity LOGIC4 is port ( A_3, A_2, A_1, A_0, B_3, B_2, B_1, B_0, CODE_IN_2, CODE_IN_1, CODE_IN_0 : in std_logic ; FLAGS_2, FLAGS_1, FLAGS_0 : inout std_logic ; Z_OUT_3, Z_OUT_2, Z_OUT_1, Z_OUT_0 : out std_logic) ; end LOGIC4 ; architecture exemplar of LOGIC4 is signal vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, vh_6, vh_7, vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, vh_32, vh_33, vh_34, vh_35, vh_36, vh_37, vh_38, vh_39, vh_40, vh_41, vh_42, vh_43, vh_45, vh_46, vh_47, vh_48, vh_49, vh_50, vh_52, vh_53, vh_54, vh_55, vh_56, vh_57, vh_58, vh_59, vh_60, vh_61, vh_62, vh_63, vh_64, vh_65, vh_66, vh_67, vh_68, vh_69, vh_70, vh_71, vh_72, vh_73, vh_74, vh_75, vh_76, vh_77, vh_78, vh_79, vh_80, vh_81, vh_82, vh_83, vh_84, vh_85, vh_86, vh_87, vh_89, vh_90, vh_91, vh_92, vh_93, vh_94, vh_95, vh_96, vh_97, vh_98, vh_99, vh_100, vh_101, vh_102, vh_103, vh_104, vh_106, vh_107, vh_108, vh_109, vh_110, vh_111, vh_112, vh_113, vh_114, vh_115, vh_116, vh_117, vh_118, vh_119, vh_120, vh_121, vh_122, vh_124, vh_125, vh_126, vh_127, vh_128, vh_129, vh_130, vh_132, vh_133, vh_134, vh_135, vh_136, vh_137: std_logic ; begin g1000 : AND3I3 port map ( Q=>vh_0, A=>B_2, B=>B_1, C=>B_0); g1001 : OR2I0 port map ( Q=>vh_1, A=>vh_0, B=>B_3); g1002 : MUX2X1 port map ( Q=>vh_2, A=>B_1, B=>B_1, S=>B_0); g1003 : AND2I0 port map ( Q=>vh_3, A=>B_0, B=>A_0); g1004 : AND2I2 port map ( Q=>vh_4, A=>vh_3, B=>A_1); g1005 : AND2I2 port map ( Q=>vh_5, A=>vh_2, B=>vh_4); g1006 : AND3I0 port map ( Q=>vh_6, A=>A_1, B=>B_0, C=>A_0); g1007 : AND2I2 port map ( Q=>vh_7, A=>vh_5, B=>vh_6); g1008 : AND2I2 port map ( Q=>vh_8, A=>B_1, B=>B_0); g1009 : MUX2X2 port map ( Q=>vh_9, A=>vh_8, B=>vh_8, S=>B_2); g1010 : AND2I1 port map ( Q=>vh_10, A=>vh_9, B=>A_2); g1011 : AND2I2 port map ( Q=>vh_11, A=>vh_7, B=>vh_10); g1012 : AND2I1 port map ( Q=>vh_12, A=>A_2, B=>vh_9); g1013 : AND2I2 port map ( Q=>vh_13, A=>vh_11, B=>vh_12); g1014 : INV port map ( Q=>vh_14, A=>vh_13); g1015 : MUX2X1 port map ( Q=>vh_15, A=>vh_0, B=>vh_0, S=>B_3); g1016 : MAJ3I0 port map ( Q=>vh_16, A=>A_3, B=>vh_14, C=>vh_15); g1017 : XNOR3I0 port map ( Q=>vh_17, A=>vh_1, B=>vh_16, C=>A_3); g1018 : AND4I1 port map ( Q=>vh_18, A=>vh_17, B=>vh_132, C=>vh_134, D=>vh_136); g1019 : AND2I1 port map ( Q=>vh_19, A=>B_1, B=>vh_4); g1020 : AND3I0 port map ( Q=>vh_20, A=>A_1, B=>B_0, C=>A_0); g1021 : AND2I2 port map ( Q=>vh_21, A=>vh_19, B=>vh_20); g1022 : AND2I2 port map ( Q=>vh_22, A=>A_2, B=>B_2); g1023 : AND2I2 port map ( Q=>vh_23, A=>vh_21, B=>vh_22); g1024 : AND2I0 port map ( Q=>vh_24, A=>B_2, B=>A_2); g1025 : AND2I2 port map ( Q=>vh_25, A=>vh_23, B=>vh_24); g1026 : INV port map ( Q=>vh_26, A=>vh_25); g1027 : MAJ3I0 port map ( Q=>vh_27, A=>A_3, B=>vh_26, C=>B_3); g1028 : MUX4X6 port map ( Q=>vh_28, A=>B_3, B=>B_3, C=>B_3, D=>B_3, S0=>A_3, S1=>vh_27); g1029 : AND3I1 port map ( Q=>vh_29, A=>vh_132, B=>vh_134, C=>vh_136); g1030 : AND5I3 port map ( Q=>vh_30, A=>vh_28, B=>vh_134, C=>vh_136, D=>vh_29, E=>vh_132); g1031 : OR2I0 port map ( Q=>FLAGS_2, A=>vh_18, B=>vh_30); g1032 : AND2I1 port map ( Q=>vh_32, A=>A_3, B=>B_3); g1033 : AND2I1 port map ( Q=>vh_33, A=>B_3, B=>A_3); g1034 : AND2I1 port map ( Q=>vh_34, A=>A_2, B=>B_2); g1035 : AND2I1 port map ( Q=>vh_35, A=>B_2, B=>A_2); g1036 : AND2I1 port map ( Q=>vh_36, A=>A_1, B=>B_1); g1037 : AND2I1 port map ( Q=>vh_37, A=>B_1, B=>A_1); g1038 : AND3I2 port map ( Q=>vh_38, A=>A_0, B=>vh_37, C=>B_0); g1039 : AND2I2 port map ( Q=>vh_39, A=>vh_36, B=>vh_38); g1040 : AND2I2 port map ( Q=>vh_40, A=>vh_35, B=>vh_39); g1041 : AND2I2 port map ( Q=>vh_41, A=>vh_34, B=>vh_40); g1042 : AND2I2 port map ( Q=>vh_42, A=>vh_33, B=>vh_41); g1043 : AND2I2 port map ( Q=>vh_43, A=>vh_32, B=>vh_42); g1044 : AND4I2 port map ( Q=>FLAGS_1, A=>vh_134, B=>vh_136, C=>vh_132, D=>vh_43); g1045 : AND3I2 port map ( Q=>vh_45, A=>B_0, B=>vh_36, C=>A_0); g1046 : AND2I2 port map ( Q=>vh_46, A=>vh_37, B=>vh_45); g1047 : AND2I2 port map ( Q=>vh_47, A=>vh_34, B=>vh_46); g1048 : AND2I2 port map ( Q=>vh_48, A=>vh_35, B=>vh_47); g1049 : AND2I2 port map ( Q=>vh_49, A=>vh_32, B=>vh_48); g1050 : AND2I2 port map ( Q=>vh_50, A=>vh_33, B=>vh_49); g1051 : AND4I1 port map ( Q=>FLAGS_0, A=>vh_136, B=>vh_132, C=>vh_134, D=>vh_50); g1052 : INV port map ( Q=>vh_52, A=>vh_136); g1053 : AND5I2 port map ( Q=>vh_53, A=>vh_50, B=>vh_134, C=>vh_132, D=>vh_43, E=>vh_52); g1054 : AND2I2 port map ( Q=>vh_54, A=>FLAGS_0, B=>vh_53); g1055 : AND5I2 port map ( Q=>vh_55, A=>vh_134, B=>vh_43, C=>vh_136, D=>vh_50, E=>vh_132); g1056 : AND3I2 port map ( Q=>vh_56, A=>vh_54, B=>FLAGS_1, C=>vh_55); g1057 : AND3I2 port map ( Q=>vh_57, A=>vh_134, B=>vh_132, C=>vh_136); g1058 : AND3I2 port map ( Q=>vh_58, A=>vh_56, B=>vh_57, C=>vh_29); g1059 : AND3I1 port map ( Q=>vh_59, A=>vh_132, B=>vh_136, C=>vh_134); g1060 : AND5I3 port map ( Q=>vh_60, A=>vh_58, B=>vh_137, C=>vh_135, D=>vh_59, E=>vh_133); g1061 : AND3I0 port map ( Q=>vh_61, A=>vh_60, B=>B_3, C=>A_3); g1062 : OR3I2 port map ( Q=>vh_62, A=>vh_55, B=>vh_54, C=>FLAGS_1); g1063 : AND4I1 port map ( Q=>vh_63, A=>vh_58, B=>vh_133, C=>vh_137, D=>vh_135); g1064 : AND2I1 port map ( Q=>vh_64, A=>FLAGS_0, B=>vh_53); g1065 : AND3I2 port map ( Q=>vh_65, A=>vh_137, B=>vh_133, C=>vh_135); g1066 : AND3I2 port map ( Q=>vh_66, A=>vh_58, B=>vh_65, C=>vh_59); g1067 : INV port map ( Q=>vh_67, A=>vh_133); g1068 : AND3I2 port map ( Q=>vh_68, A=>vh_133, B=>vh_135, C=>vh_137); g1069 : AND5I3 port map ( Q=>vh_69, A=>vh_66, B=>vh_67, C=>vh_137, D=>vh_68, E=>vh_135); g1070 : AND4I3 port map ( Q=>vh_70, A=>vh_62, B=>vh_63, C=>vh_64, D=>vh_69); g1071 : AND2I1 port map ( Q=>vh_71, A=>A_3, B=>vh_70); g1072 : OR2I2 port map ( Q=>vh_72, A=>vh_54, B=>vh_55); g1073 : AND4I2 port map ( Q=>vh_73, A=>vh_66, B=>vh_133, C=>vh_137, D=>vh_135); g1074 : AND4I1 port map ( Q=>vh_74, A=>vh_58, B=>vh_133, C=>vh_137, D=>vh_135); g1075 : AND4I3 port map ( Q=>vh_75, A=>vh_72, B=>vh_73, C=>vh_74, D=>vh_53); g1076 : AND2I1 port map ( Q=>vh_76, A=>B_3, B=>vh_75); g1077 : INV port map ( Q=>vh_77, A=>vh_21); g1078 : MAJ3I0 port map ( Q=>vh_78, A=>A_2, B=>vh_77, C=>B_2); g1079 : MUX4X6 port map ( Q=>vh_79, A=>B_3, B=>B_3, C=>B_3, D=>B_3, S0=>A_3, S1=>vh_78); g1080 : AND5I3 port map ( Q=>vh_80, A=>vh_56, B=>vh_135, C=>vh_137, D=>vh_29, E=>vh_133); g1081 : AND2I0 port map ( Q=>vh_81, A=>vh_79, B=>vh_80); g1082 : OR3I0 port map ( Q=>vh_82, A=>B_2, B=>B_1, C=>B_0); g1083 : XNOR3I0 port map ( Q=>vh_83, A=>vh_82, B=>A_3, C=>B_3); g1084 : MUX2X2 port map ( Q=>vh_84, A=>vh_13, B=>vh_13, S=>vh_83); g1085 : AND4I1 port map ( Q=>vh_85, A=>vh_56, B=>vh_133, C=>vh_135, D=>vh_137); g1086 : AND2I0 port map ( Q=>vh_86, A=>vh_84, B=>vh_85); g1087 : AND3I3 port map ( Q=>vh_87, A=>vh_76, B=>vh_81, C=>vh_86); g1088 : OR3I1 port map ( Q=>Z_OUT_3, A=>vh_61, B=>vh_71, C=>vh_87); g1089 : AND3I3 port map ( Q=>vh_89, A=>vh_21, B=>A_2, C=>B_2); g1090 : MUX2X2 port map ( Q=>vh_90, A=>B_2, B=>B_2, S=>A_2); g1091 : AND2I0 port map ( Q=>vh_91, A=>vh_90, B=>vh_21); g1092 : AND2I2 port map ( Q=>vh_92, A=>vh_89, B=>vh_91); g1093 : AND2I1 port map ( Q=>vh_93, A=>vh_80, B=>vh_92); g1094 : AND2I1 port map ( Q=>vh_94, A=>vh_80, B=>vh_21); g1095 : AND2I2 port map ( Q=>vh_95, A=>vh_60, B=>vh_94); g1096 : AND2I1 port map ( Q=>vh_96, A=>B_2, B=>vh_95); g1097 : AND2I1 port map ( Q=>vh_97, A=>vh_70, B=>vh_96); g1098 : AND2I1 port map ( Q=>vh_98, A=>A_2, B=>vh_97); g1099 : OR2I0 port map ( Q=>vh_99, A=>B_1, B=>B_0); g1100 : XNOR3I0 port map ( Q=>vh_100, A=>B_2, B=>A_2, C=>vh_99); g1101 : MUX2X2 port map ( Q=>vh_101, A=>vh_7, B=>vh_7, S=>vh_100); g1102 : AND2I0 port map ( Q=>vh_102, A=>vh_101, B=>vh_85); g1103 : AND2I1 port map ( Q=>vh_103, A=>B_2, B=>vh_75); g1104 : AND2I2 port map ( Q=>vh_104, A=>vh_102, B=>vh_103); g1105 : OR3I1 port map ( Q=>Z_OUT_2, A=>vh_93, B=>vh_98, C=>vh_104); g1106 : AND3I2 port map ( Q=>vh_106, A=>vh_80, B=>B_1, C=>A_1); g1107 : XOR3I0 port map ( Q=>vh_107, A=>B_1, B=>A_1, C=>B_0); g1108 : AND2I1 port map ( Q=>vh_108, A=>vh_85, B=>vh_107); g1109 : AND2I2 port map ( Q=>vh_109, A=>vh_106, B=>vh_108); g1110 : AND2I1 port map ( Q=>vh_110, A=>vh_3, B=>vh_109); g1111 : AND2I0 port map ( Q=>vh_111, A=>vh_3, B=>vh_80); g1112 : AND2I2 port map ( Q=>vh_112, A=>vh_60, B=>vh_111); g1113 : AND2I1 port map ( Q=>vh_113, A=>B_1, B=>vh_112); g1114 : AND2I1 port map ( Q=>vh_114, A=>vh_70, B=>vh_113); g1115 : AND2I1 port map ( Q=>vh_115, A=>A_1, B=>vh_114); g1116 : MUX2X2 port map ( Q=>vh_116, A=>B_1, B=>B_1, S=>A_1); g1117 : AND2I0 port map ( Q=>vh_117, A=>vh_116, B=>vh_80); g1118 : AND2I0 port map ( Q=>vh_118, A=>vh_85, B=>vh_107); g1119 : AND2I2 port map ( Q=>vh_119, A=>vh_117, B=>vh_118); g1120 : AND2I2 port map ( Q=>vh_120, A=>vh_3, B=>vh_119); g1121 : AND2I1 port map ( Q=>vh_121, A=>B_1, B=>vh_75); g1122 : AND2I2 port map ( Q=>vh_122, A=>vh_120, B=>vh_121); g1123 : OR3I1 port map ( Q=>Z_OUT_1, A=>vh_110, B=>vh_115, C=>vh_122); g1124 : MUX2X1 port map ( Q=>vh_124, A=>B_0, B=>B_0, S=>A_0); g1125 : AND2I2 port map ( Q=>vh_125, A=>vh_80, B=>vh_85); g1126 : OR2I0 port map ( Q=>vh_126, A=>vh_124, B=>vh_125); g1127 : AND2I1 port map ( Q=>vh_127, A=>A_0, B=>vh_70); g1128 : AND2I0 port map ( Q=>vh_128, A=>vh_3, B=>vh_60); g1129 : AND2I1 port map ( Q=>vh_129, A=>B_0, B=>vh_75); g1130 : AND4I3 port map ( Q=>vh_130, A=>vh_126, B=>vh_127, C=>vh_128, D=>vh_129); g1131 : INV port map ( Q=>Z_OUT_0, A=>vh_130); g1132 : BUFF port map ( Q=>vh_132, A=>CODE_IN_0); g1133 : BUFF port map ( Q=>vh_133, A=>CODE_IN_0); g1134 : BUFF port map ( Q=>vh_134, A=>CODE_IN_2); g1135 : BUFF port map ( Q=>vh_135, A=>CODE_IN_2); g1136 : BUFF port map ( Q=>vh_136, A=>CODE_IN_1); g1137 : BUFF port map ( Q=>vh_137, A=>CODE_IN_1); end exemplar ;